The temp grade is C and speed grade is -1. The Xilinx FPGA device on Basys 3 is Artix 7 a35T. In this case, I saved under the file under the 3_bit_counter projectĬhoose the right device. ![]() Click “Add File” and then find out where you save the master xdc file. ![]() You can download the Basys 3 master xdc file from Digilent. The counter and top module will be created later.Ĭlick “OK” and you will see a “clkdivider” file has been createdĬlick “Next” as we don’t have any IP in the projectĬlick “+” to add constraints in the project. We will have three modules – clock divider, counter and top moudle. As we don’t have any pre-built module, so we just click “+” and create fileĬhoose file type Verilog and name it as “clkdivider”. RTL is called register transfer level.Ĭlick “Next” and then add sources. I name the project as 3_bit_counter and put that under my C driveĬlick “Next” and choose the project. Name the the project and choose the project location. Thenclick “Create New Project”Ĭlick “Next”. ![]() However, I will still go through that very briefly.įirst, open Vivado Webpack. You can follow the getting started guide to create a new project.
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